The present invention relates to a technique effective for application to a method of applying a write voltage in an electrically erasable programmable nonvolatile memory, and a technique effective for use in a flash memory capable of erasing data in a lump, for example, on a block unit basis and a microcomputer having therein the flash memory.
A flash memory uses a nonvolatile memory cell taking the form of a MOSFET of a two-layer gate structure having a control gate and a floating gate, and a memory cell can be constructed by a single transistor. Conventional methods of writing data into a flash memory include a method of changing a threshold voltage by injecting or discharging charges to/from a floating gate by using an FN tunnel phenomenon by applying a voltage across the control gate and a substrate (what is called a well region) or across the control gate and a source or drain, and a method of changing a threshold voltage by passing a current between the source and the drain in a state where a high voltage is applied to the control gate and injecting hot electrons generated in a channel into the floating gate and discharging charges from the floating gate by using the FN tunnel phenomenon.
According to the writing method using the FN tunnel phenomenon, a write current is low, so that data can be written on a word line unit basis of, for example, 128 bytes. The method has an advantage such that data can be written in a lump. On the other hand, according to the writing method using hot electrons, a write current is high and it is difficult to write data in a lump on the word line unit basis, so that data is written on the basis of a unit such as one byte. It is difficult to reduce the size of a memory cell employing the writing method using the FN tunnel phenomenon in relation to a withstand voltage and the packing density does not therefore increased.
In any of the above writing methods, in many cases, data in a flash memory is erased on a block unit basis, that is, data in a plurality of sectors commonly using a well region is simultaneously erased.
The inventors herein have examined in detail a technique of shortening the write time in a flash memory employing the writing method using hot electrons. In the case of the writing method using hot electrons, a write voltage is applied to a memory cell only with respect to a bit of which write data is xe2x80x9c0xe2x80x9d, and no write voltage is applied to a memory cell with respect to a bit of which write data is xe2x80x9c1xe2x80x9d. The inventors got an idea of shortening the write time as a whole by skipping the writing operation on the bit of which write data is xe2x80x9c1xe2x80x9d.
An example of a conventional method of shortening the write time in a flash memory employing the writing method using hot electrons is a method of overlapping write pulses by shifting a timing of writing data to a bit little by little (proposed in Japanese Unexamined Patent Application Nos. 5-62484, 5-325574, and 4-38700). By the method of shifting the write timing little by little, the write time becomes certainly shorter as compared with the method of sequentially writing data bit by bit. However, since the writing operation is performed (write cycle is included) even in the case where write data is xe2x80x9c1xe2x80x9d and it is unnecessary to apply a voltage, time is wasted. In addition, a write current largely fluctuates depending on a write data pattern, that is, whether there are many bits of xe2x80x9c0xe2x80x9d or not. Consequently, in the case where a booster circuit for generating a write voltage is provided on the inside, there is a problem such that a voltage generated by the booster circuit is vulnerable to fluctuations and a stable writing operation cannot be performed.
An object of the invention is to provide a nonvolatile memory with a shortened write time as a total and a semiconductor integrated circuit such as a microcomputer having therein the nonvolatile memory.
Another object of the invention is to provide a nonvolatile memory capable of performing a stable writing operation by making a write current constant and reducing fluctuations in a voltage generated by a booster circuit and a semiconductor integrated circuit such as a microcomputer having therein the nonvolatile memory.
The above and other objects and novel features of the invention will become apparent from the description of the specification and the appended drawings.
Representative ones of inventions disclosed in the application will be briefly described as follows.
In a nonvolatile memory such as a flash memory employing the writing method using hot electrons, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic xe2x80x9c1xe2x80x9d (or logic xe2x80x9c0xe2x80x9d), the writing operation is successively performed on bits corresponding to write data having the logic xe2x80x9c0xe2x80x9d (or logic xe2x80x9c1xe2x80x9d).
More concretely, a nonvolatile memory of the invention includes: a memory array having a plurality of word lines, a plurality of bit lines, and a plurality of nonvolatile memory cells, in which control terminals of nonvolatile memory cells in the same row are connected to a common word line, and data input/output terminals of the nonvolatile memory cells in the same column are connected to a common bit line; a data register for holding write data of the plurality of nonvolatile memory cells; and a write control circuit for applying a write voltage to the bit line in accordance with write data held in the data register. The nonvolatile memory is constructed to store data by changing a threshold voltage of the nonvolatile memory cell by applying the write voltage to the bit line. When a bit corresponding to write data held in the data register has logic xe2x80x9c1xe2x80x9d (or logic xe2x80x9c0xe2x80x9d), the write control circuit skips the bit and sequentially applies the write voltage to bit lines corresponding to the bit having the logic xe2x80x9c0xe2x80x9d (or logic xe2x80x9c1xe2x80x9d).
According to the means, data is determined at the time of writing operation and the total write time can be shortened only by the write time of bits corresponding to the write data having the logic xe2x80x9c1xe2x80x9d (or logic xe2x80x9c0xe2x80x9d). Since the data writing operation is executed in each of the cycles, that is, there is no cycle in which the writing operation is not performed, as compared with the conventional method, fluctuations in the write current are reduced. Thus, the stable writing operation can be performed with suppressed fluctuations in the voltage generated by a booster circuit.
Desirably, the write voltage is applied in parallel to two or more bit lines to which the write voltage is to be applied. With the configuration, as compared with the method of writing data bit by bit, the total write time is shortened.
Preferably, the number of bit lines (the number of overlap write pulses) to which the write voltage is applied in parallel is constructed to be changeable. With the configuration, by changing the number of write voltages to be applied in parallel in accordance with variations in the circuit or the like, the capability of the booster circuit for generating the write voltage can be effectively used.
In the configuration, a register for setting a value for designating the number of bit lines to which the write voltage is applied in parallel is provided. With the configuration, only by setting the value of the register by the CPU or the like, the number of write voltages can be easily changed.
Further, application time per time of the write voltage is constructed to be changeable. With the configuration, by changing the application time of write voltages to be applied in parallel in accordance with the characteristics of the like of the memory cell, the optimum writing operation can be finished in the shortest time.
Preferably, the application time of the write voltage is determined on the basis of a clock signal, and the cycle of the clock signal is changed to thereby change the application time of the write voltage. Consequently, the change in the application time of the write voltage can be realized by the simple method of changing the cycle of the clock signal. More concretely, a variable frequency dividing circuit capable of generating the clock signals of different cycles on the basis of a reference clock signal and a register for setting a value of designating a frequency dividing ratio in the variable frequency dividing circuit are provided. By changing the frequency driving ratio, the cycle of the clock signal is changed. With the configuration, the nonvolatile memory capable of easily changing the application time of the write voltage can be realized. A value set in the register for setting the value of designating the number of bit lines to which the write voltage is applied in parallel and a register for setting a value of designating the frequency dividing ratio in the variable frequency dividing circuit may be stored in a predetermined memory cell in the nonvolatile memory.
Further, a shift register for sequentially outputting the write voltage on the basis of the clock signal and write data held in the data register is provided. With the configuration, only by setting the value of the register by the CPU or the like, the application time of the write voltage can be easily changed.
The shift register is constructed to perform a shifting operation synchronously with one of two clock signals of phases different from each other, the clock signal to be supplied is switched between the two clock signals in accordance with the write data held in the data register and, when the bit of the write data has the logic xe2x80x9c1xe2x80x9d (or logic xe2x80x9c0xe2x80x9d), the bit is skipped, and the write voltage is sequentially applied to bit lines corresponding to a bit having the logic xe2x80x9c0xe2x80x9d (or logic xe2x80x9c1xe2x80x9d).
Alternately, the shift register includes a through path and a shift path for each of shift stages and switching means for switching the path between the through path and the shift path and performs a shifting operation synchronously with the clock signal, the switching means switches the path between the through path and the shift path in accordance with the write data held in the data register and, when the bit of the write data has the logic xe2x80x9c1xe2x80x9d (or logic xe2x80x9c0xe2x80x9d), the bit is skipped and the write voltage is sequentially applied to bit lines corresponding to a bit having the logic xe2x80x9c0xe2x80x9d (or logic xe2x80x9c1xe2x80x9d).
Further, distributing means is provided between the shift register and the bit line, for enabling the write voltage to be applied to one of a plurality of bit lines on the basis of an output signal of each of the shift stages of the shift register. The data register can hold write data of the number of bits corresponding to the number of bit lines and, between the shift register and the shift register, selecting means for selecting one of the plurality of bits of the data register and supplying the selected bit to any of the shift stages of the shift register is provided. With the configuration, each of the stages of the shift register can be shared by the plurality of bit lines. Thus, by decreasing the number of stages of the shift register, the circuit is simplified and the layout is facilitated.
Further, the write voltage is applied once to the plurality of bit lines. After completion of the writing operation on a plurality of memory cells connected to one word line, for verification, data is read from a memory cell connected to the word line including the memory cell on which the writing operation has been performed. When a memory cell on which the writing operation has not been performed yet exists, the write voltage is sequentially applied only to the bit line to which the memory cell on which the writing operation has not been performed yet is connected for a time different from an application time of the write voltage applied in the preceding writing operation.
Alternately, the data reading operation for verification is performed. After that, when the memory cell on which the writing operation has not been performed yet is found, a write voltage different from the write voltage applied in the preceding writing operation is sequentially applied to the bit line to which the memory cell on which the writing operation has not been performed yet is connected. By the operation, the threshold can be prevented from being largely changed more than required due to excessive writing operation.
Preferably, when the memory cell on which the writing operation has not been performed yet is found by the data reading operation for verification, a write voltage different from the write voltage applied in the preceding writing operation is sequentially applied to the bit line to which the memory cell on which the writing operation has not bee performed yet is connected, and the number of write voltages to be applied in parallel to the plurality of bit lines is changed from that in the preceding writing operation.